bids are invited for xj runner with pxi xjlink 2.0suite a) pxi-xjlink2+ xjrunner should consist of boundary scan applications (software)- xjrunner b) it consists of following (hardware): pxi-xjlink2with h/w license should have run-time environment for xjease tests. should have fault dictionary to capture and board statistics and fault trend analysis. should have xjintegration software which allows control of xjrunner from other test systems should be able to execute all the tests developed in xjdeveloper in simple, controlled test execution window should have 32-bit pxi/cpci bus interface with 3u form factor. should support ni labview virtual instruments (vis) should be able to connect to up to 4 jtag chains on the uut with configurable functionality for all i/o pins and tck clock frequencies up to 166 mhz. should be able to configure to two different voltages, from 1.1 v to 3.3 v in 0.1 v steps. should support simple dll api interface: includes commands such as tmsreset() irscan() drscan() etc. . should have visual indication of test status. should support adjustable jtag signal termination and automatic signal total quantity : 1