BRR : 4862663
Tender Brief : Bids Are invited for Software Licenses-UEF-VIVADO-ENETER-25 + UEF-MATSIM-ADDON-25 - Part1 - Vivado ML Enterprise Edition +Vitis Model Composer Plugin, University License- 25 License of Latest version , TUL PYNQ-Z2 board along with accessories(1M1-M000127DVA- Part 2) - ZYNQ XC7Z020-1CLG400C650MHz dual-core Cortex-A9 processor ,DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports, High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO , Low-bandwidth peripheral controller: SPI, UART, CAN, I2C, Programmable from JTAG, Quad-SPI flash, and microSD card, Pro... Read More
Tender Value
Ref. Document
Contract Value
₹ 4,65,297
Submission Date
29-11-2021
Contract Date
Ref. Document
Completion Date
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Participated Bidder List
1 No of Bidder(s)
Sr No. Bidder Name Bid Analytics Technical Bid Financial Bid AOC Bid Value Rank
1 cnet-technologies Bid Analytics 4,65,297 L1
Work Detail
bids are invited for software licenses-uef-vivado-eneter-25 + uef-matsim-addon-25 - part1 - vivado ml enterprise edition +vitis model composer plugin, university license- 25 license of latest version , tul pynq-z2 board along with accessories(1m1-m000127dva- part 2) - zynq xc7z020-1clg400c650mhz dual-core cortex-a9 processor ,ddr3 memory controller with 8 dma channels and 4 high performance axi3 slave ports, high-bandwidth peripheral controllers: 1g ethernet, usb 2.0, sdio , low-bandwidth peripheral controller: spi, uart, can, i2c, programmable from jtag, quad-spi flash, and microsd card, programmable logic equivalent to artix-7 fpga, 13,300 logic slices, each with four 6-input luts and 8 flip-flops, 630 kb of fast block ram, 4 clock management tiles, each with a phase locked loop (pll) and mixed-mode clock manager (mmcm),220 dsp slices, on-chip analog-to-digital converter (xadc) , arty a7-100: artix-7 fpga development board (410-319-1 - part 3) - xc7a35ticsg324-1l33,280 logic cells in 5200 slices (each slice contains four 6-input luts and 8 flip-flops), 1,800 kbits of fast block ram; o five clock management tiles, each with a phaselocked loop (pll), 90 dsp slices, internal clock speeds exceeding 450mhz, on-chip analog-to-digital converter (xadc), programmable over jtag and quad-spi flash , spartan-7 sp701 fpga evaluation kit (ek-s7-sp701-g-part4) - xcs7100102,400 logic cells in 16000 slices (each slice contains four 6-input luts and 8 flip-flops), 1,800 kbits of fast block ram; o five clock management tiles, each with a phase locked loop (pll), 160 dsp slices, i2c programmable sysclk oscillator 33.33 mhz, on-chip analog-to-digital converter (xadc), programmable over jtag and quad-spi flash , digilent 410-370 development board (410-370-part5 ) - xc7z010-1clg400c 35200 flip-flops, 80 dsp slices, 270 kb block ram, 17600 look up tablesxc7z007s-1clg400c, 28800 flip-flops, 66 dsp slices, 225 kb block ram, 14400 look up tables667mhz cortex-a9 processor (dual core), on chi
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Download 2494b7aa-57be-4a6e-abb9-2755c8915986
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Download 9182cc4b-a730-4310-b45d-e696107bb34f Tender Documents
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Awarded Bidder(s)
1
cnet-technologies
Rank : L1 (Lowest)
Bid Amount : ₹ 1,00,00,000
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