bids are invited for lab apparatus 1 15 -verification and interpretation of truth table for and, or, not, nand, nor and exor gates. , to design a half adder and full adder using gates and verification of their operation construction of a full adder circuit using xor and nand gates and verify its operation. , to design a half subtractor and full subtractor circuit with the help of gates and verify their operation , 4 bit adder subtractor circuit using an ic verify the operation. , verification of truth table of jk and jk master slave flip flops. , steps to enter, modify data program and to execute a program on 8085 kit. , writing and execution of alp for addition and subtractions of two 8 bit numbers. , writing and execution of alp for multiplication and division of two 8 bit numbers. , writing and execution of alp for arranging 10 numbers in ascending descending order. , verify of truth table for decoder ics , to design a 4 bit siso, sipo, piso, pipo shift register using jk d flip flop and verification of their operation , design decode counter and its verification. , design analog to digital and digital to analog converters and their verification. , to design a 4 bit binary counter and verify its truth table. , to determine the output of rl, rc, rlc series and parallel circuit. , transient response in r-l and r-c network , transient response in r-l-c series and parallel circuits network , determination of impedance z and admittance y parameters of two port network , verification of kirchhoff current and voltage laws applied to dc circuit , to construct an rl and rc circuit and to measure impedance, phase angle total quantity : 40