Supply Of Evaluation Kit Core Soc
Tender Overview
Project Description
Supply Of Evaluation Kit Core Soc; Logic Cells (K)-85 • Support 32 data width • 33.33MHz Fixed PS System Oscillator (Single-Ended CMOS) clocking • DSP Slices-220 • PC4 and 20 pin JTAG ports • 200MHz Fixed PL Oscillator (Differential LVDS) clocking • 16MB Quad SPI Flash memory • 156.25MHz (default) I2C Programmable Oscillator clock (Differential LVDS) • IIC - 1 KB EEPROM memory • DDR3 Component Memory • Maximum I/0 Pins-200. • 8 LED Indication • 12V power supply 2. Installation
AI Tender Summary
Tender Timeline
Tender Published
Tender notice published.
CompletedBid Submission Deadline
Offline submission at the designated office.
CompletedBid Opening Date
Technical bids will be opened and evaluated.
CompletedTender Documents
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