Tender For Hil System

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Tender For Hil System; 1 HIL SYSTEM Logic Elements Minimum 444000 Logic Elements DSP Slices Minimum 2020 Block RAM Minimum 26 Mb 2 DDR3 Memory Memory Size Minimum 1 GB (32b Access) 3 Quad SPI Flash Memory Memory Size 16 MB 4 Micro SD Memory Card Included in hardware 2 Cards Included in hardware 32 GiB each A Stand-alone user interfaces for real time system 1 Self-Sufficient Model-Based Design Platform External PC or Software Requirement No additional PC or external software required for creating model-based design 2 Editable ModelBased Design During Runtime Runtime Editability Design can be edited for adding new elements or removing existing elements without stopping the running design 3 Configurable Protection Logic with Rapid Response Response Time Protection logic configurable in modelbased design; all system outputs default to safe state within 1 µs 4 Indigenous BareMetal OS for Security OS Security Bare-metal OS ensures high security and nontraceable application design 5 Integrated Development and Deployment Platform Platform Consistency Development platform and deployment target are the same, allowing instant compilation of design changes 6 HDMI Resolution and Refresh Rate Full HD 1920x1080, 60Hz 7 USB4 ports USB ports type A, B, C 2 unit each (So, total 6 ports) 8 FULL HD Monitor Size and Resolution 32 inch, 1920x1080 minimum 9 Necessary connector cables Included Yes B Built in IP cores 1 HDMI Interface Controller Resolution and Refresh Rate Full HD 1920x1080, 60Hz 2 USB Keyboard Interface Controller IP Core counts 1 3 USB Mouse Interface Controller IP Core counts 1 4 DDR3 Interface Controller Memory size 1 GiB 5 Micro SD Memory Interface Controller 4-bit SD Mode, 16 GB card access 2 6 Gigabit Ethernet UDP IP Controller IP Core counts 1 7 Floating Point Processor IP Cores 2Kx48b program mem, 2Kx32b data IEEE754 FP Instructions 25 C Model based design framework directly operatable as bare metal inside Real time system 1 User Configuration Number of Users Minimum 4 2 Database Support Number of Files Minimum 64 3 Model Development GUI Page Size 4096 x 4096 pixels Hierarchical Submodules Support for 15 parallel submodule GUIs 4 Dedicated Control Input for Each Submodule Ability to Run/Stop Blocks using Control logics Yes 5 Dedicated Design Window for Each Processor IP Page Size 4096 x 4096 pixels D IO Interfaces for real time system 1 Digital Outputs 5V Logic Level Group isolated, 36 channels (6 channels per group) 2 Digital Inputs 5V Logic Level Group isolated, 18 channels (6 channels per group) 3 DAC Analog Outputs +/- 10V outputs, singleended, 16 bits, 100 KS per second, group isolated 16 channels as group isolated 4 ADC Analog Inputs / Voltage Sensors +/- 10V outputs, singleended,16 bits, 500 KS per second, Independently isolated 32 channels independently isolated 5 USB RS232 Ports USB RS232 Ports 1 6 DB9 RS232 Ports DB9 RS232 Ports 2 7 DB9 RS422 Ports DB9 RS422 Ports 2 8 Giga Bit Ethernet Port Giga Bit Ethernet Port 1 E Document desk 1 Data Samples Internal logging and Export Format and Speed Export to .CSV file via USB serial port, 8 channels x 1 million samples, max speed of 10 µs 2 Data Samples Import Format and Speed Import from .CSV file via USB serial port, max speed of 10 µs 3 Document Desk Data Log Table View 8 channels x 1 million samples F Data Logging & Data Source 1 Real time data logging with Ethernet Output Streaming Gigabit Ethernet Data Transmission Stream design samples to PC via Gb Ethernet port PC Application Logging data via Gb Ethernet port in PC as .CSV file 2 Real time data source with Ethernet Input Streaming Gigabit Ethernet Data Reception Source samples from PC via Gb Ethernet port .... more in document