Tender For Embedded Data Processing Module, bengaluru-Karnataka

Tender For Embedded Data Processing Module; 1 Electrical Interface Data Y 2 Mechanical envelope requirements Y 3 Thermal specification at package interface Y 4 ESD specification Y 5 Grounding scheme post PO release Y 6 ICD for non-standard interface & updated EID post PO release Y 7 Schematic (includes netlist, max frequency of operation, expected voltage and current per net, differential pairs) in Cadence ORCAD compatible .dsn file format. Y 8 Schematic review and acceptance Y 9 Gate review at vendor level and ISRO level Y Y Design phase 10 PCB layout design Y 11 Mechanical design, connector selection & mechanical drawing Y 12 All Analysis listed in design phase Y 13 Gate review at vendor level and ISRO level Y Y Engineering model realisation Phase 14 Component procurement for EMs Y 15 Package fabrication (engineering model) Y 16 Board power-up, verification and validation all interfaces at maximum capacity. All internal nets have to be energised during testing. Y 17 Individual cards testing and clearance for package assembly at vendor premises Y Y 18 Tested cards assembling as package, tested after assembly and delivery to ISRO along with one test-jig Y 19 Package level review for clearance of first EM Y Y 20 Based on review findings, required design corrections implementation Y 21 Delta review for the implemented changes Y Y 22 Delivery to ISRO of the tested and verified second EM and QM subsequent to implementing changes suggested from delta review (Testing and verification shall be at vendor premises). Test-jig updates (if any) shall be carried out at ISRO premises by vendor. Y 23 Package level review to clear for Part-A closure Y Y 1 Electrical Interface Data Y 2 Suggested BoM (includes part number, quality of component, expected thermal dissipation for high dissipating components) Y 3 Mechanical envelope requirement Y 4 Stiffness, Quasi Static Load, Shock Level Y 5 Vibration (Sine & Random) specification for the package Y 6 Thermal specification at package interface Y 7 Vacuum specification Y 8 Outgassing (RML & CVCM) requirement Y 9 ESD specification Y 10 EMI EMC specification Y 11 Grounding scheme post PO release Y 12 ICD for non-standard interface & updated EID post PO release Y 13 Schematic (includes component finalisation, netlist, max frequency of operation, expected voltage and current per net, differential pairs) in Cadence ORCAD compatible .dsn file format. Y 14 Schematic review and vendor acceptance Y 15 Gate review at vendor level and ISRO level Y Y Design phase 16 PCB layout design Y 17 Mechanical design, connector selection & mechanical drawing Y 18 All Analysis listed in design phase Y 19 Gate review at vendor level and ISRO level Y Y Engineering model realisation Phase 20 Component procurement for EMs Y 21 Package fabrication (engineering model) Y 22 Board power-up, verification and validation all interfaces at maximum capacity. All internal nets have to be energised during testing. Y 23 Individual cards testing and clearance for package assembly at vendor premises Y Y 24 Tested cards assembling as package, tested after assembly and delivery to ISRO along with one test-jig Y 25 Package level review for clearance of first EM Y Y 26 Based on review findings, required design corrections implementation Y 27 Delta review for the implemented changes Y Y 28 Realisation of second EM and QM subsequent to changes along with delivery of second EM Y 29 Flight qualification campaign tests and validation using QM Y 30 Validation of test results and subsequent delivery of QM to URSC Y Y 31 Package level review to clear for project closure Y Y

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