Tender For Purchase Of Fpga Trainer Kit To The Hardware Design Lab Under The Division Of It, Soe, Cochin University Of Science & Technology, Kochi-

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Tender For Purchase Of Fpga Trainer Kit To The Hardware Design Lab Under The Division Of It, Soe, Cochin University Of Science & Technology, Kochi- 33,280 logic cells in 5200 slices (each slice contains four 6 input LUTs and 8 flip-flops) 1800 Kbits of fast block RAM Five clock management tiles, each with a phase- locked loop(PLL) 90 DSP slices Internal clock speeds exceeding 450 MHz On-Chip analog-to-digital converter (XADC) 16 user switches,16 user LEDs 5 user push buttons 4 – digit 7 – segment display 4 Pmod connectors, 3 standard 12 pin Pmod 1 dual purpose XADC signal/ standard Pmod 12 bit VGA output USB-UART Bridge Serial Flash USB-JTAG port for FPGA programming and communication. USB HID Host for mice, keyboards and memory sticks. Total quantity required : Five numbers of Kit.