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Bids Are Invited For Pxi System And Usb Daq (Q3) Total Quantity : 1, Kanpur Nagar-Uttar Pradesh

Department of Higher Education has published Bids Are Invited For Pxi System And Usb Daq (Q3) Total Quantity : 1. Submission Date for this Tender is 23-02-2024. Personal Computers Tenders in Kanpur Nagar Uttar Pradesh. Bidders can get complete Tender details and download the document.




Tender Notice

41900910
Corrigendum : Bids Are Invited For Pxi System And Usb Daq (Q3) Total Quantity : 1
Tender
Indian
Uttar Pradesh
Kanpur Nagar
23-02-2024

Tender Details

Bids Are Invited For Pxi System And Usb Daq -1 PXI Controller CPU: Intel® Core™ i3 4110E (2.6 GHz dual-core processor) On-die last level cache: 3 MB Single-Channel: 1600 MHz DDR3L RAM, PC3 12800 -2 GB standard, 8 GB maximum Hard Drive: 320 GB Serial ATA, minimum Ethernet: One 10/100/1000 Base T port PXI Express 4 Link Configuration: x1, x1, x1, x1 PXI Express 2 Link Configuration: x1, x1 Serial Port (RS-232): Yes Hi-Speed USB (2.0) Ports: Yes SuperSpeed USB (3.0) Ports: Yes Express Card/34 Slot: No PXI Trigger Bus Input/Output: Yes Installed Operating System: Windows 7 Professional for Embedded Systems 1 2 PXI Module Number of channels Analog Input: 8 differentials ADC resolution: 16 bits Sample rate: 1.25 MS/s/Ch Timing resolution: 10 ns Timing accuracy: 50 ppm of sample rate Input coupling: DC Input range: ±1 V, ±2 V, ±5 V, ±10 V 3 PXI Chassis Chassis Type: PXIe Slot Type: Hybrid Slots No of Slot: 4 Slot Hybrid Slots: 3 Slot Maximum System Bandwidth: 3 GB/s Input voltage range: 100 to 240VAC Operating voltage range: 90 to 264VAC Input current rating: 4 to 2 A Input frequency: 50/60 Hz Per slot cooling capacity: 38.25 W Module cooling system: Forced air circulation (positive pressurization) through a 150-cfm fan with High/Auto speed selector Slot airflow direction: Bottom of module to top of module 1 4 Accessories SCB-68A Noise Rejecting, Shielded I/O Connector Block 1 SHC68-68-EPM Shielded Cable, 68-D-Type to 68 VHDCI Offset, 2 m 1 Power Cord, 250V, 10A, India 1 5 USB DAQ Number of channels: 8 differentials ADC resolution: 16 bits Sample rate simultaneous: 500 kS/s Timing resolution: 10 ns Timing accuracy: 50 ppm of sample rate Input coupling: DC Input range: ±1 V, ±2 V, ±5 V, ±10 V CMRR (at 60 Hz): 80 dB Bandwidth (small signal): 2.0 MHz at ±1 V & 2.9 MHz at other ranges Input bias current: ±6 nA & ±90 nA Input FIFO size: 32 MS shared among channels used Data transfers: USB Signal Stream, programmed I/O Number of triggers: 1 Source: AI <0..7>, APFI 0 Functions: Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Sample Clock Timebase Resolution: 16 bits Analog Output: 2 DAC resolution: 16 bits DNL: ±1 LSB, maximum Monotonicity: 16 bit guaranteed Maximum update rate (simultaneous): 1 channel -900 kS/s; 2 channels - 840 kS/s Output range: ±10 V Output coupling: DC Output impedance: 0.2 Ω Output current drive: ±5 mA Overdrive protection: ±15 V Overdrive current: 15 mA Power-on state: ±20 mV Digital I/O/PFI: 24 total ( Q3 ) Total Quantity : 1

Corrigendum Details

Sr No CorrigendumDate Corrigendum CorrigendumType NewSubmissionDate
1 20-02-2024 23-02-2024

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