Educational and Research Institute Government Departments Closing in 0 days TDR #22677987

Supply Of Fpga Boards For Vlsi Design Laboratory

Issued by Government Departments · GOVERNMENT COLLEGE OF ENGINEERING BODINAYAKKANUR, Tamil Nadu
Tender Value
Ref. Documents
Estimated cost
Bid Submission
13 Dec 2019
0 days left
EMD
Ref. Documents
Bank guarantee accepted
Document Fee
Ref. Documents
Non-refundable
Tender Type
Online

Tender Overview

Competition Type
NCB
Bidding Type
Tender
Location / State
GOVERNMENT COLLEGE OF ENGINEERING BODINAYAKKANUR → Tamil Nadu
EMD Exemption
Not Available
Quantity
Not Available

Project Description

Supply Of Fpga Boards For Vlsi Design Laboratory - 1. 33, 280 Logic Cells In 5200 Slices ( Each Slice Contains Four 6-Input Luts And 8 Flip-Flops ) 2. 1, 800 Kbits Of Fast Block Ram 3. Five Clock Management Tiles, Each With A Phase-Locked Loop ( Pll ) 4. 90 Dsp Slices 5. Internal Clock Speeds Exceeding 450 Mhz 6. On-Chip Analog-To-Digital Converter ( Xadc ) 7. Usb-Jtag Port For Fpga Programming And Communication 8. Serial Flash 9. Usb-Uart Bridge 10. 12-Bit Vga Output 11. Usb Hid Host For Mice, Keyboards And Memory Sticks 12. 16 User Switches 13. 16 User Leds 14. 5 User Push Buttons 15. 4-Digit 7-Segment Display, 4 Pmod Ports: 3 Standard 12-Pin Pmod Ports, 1 Dual Purpose Xadc Signal / Standard Pmod Port.

AI Tender Summary

OUR REF NO 22677987
AUTHORITY Government Departments
TENDER VALUE Ref. Documents
LAST DATE 13-12-2019
Authority
Authority Name Government Engineering College
Work Description Supply Of Fpga Boards For Vlsi Design Laboratory - 1. 33, 280 Logic Cells In 5200 Slices ( Each Slice Contains Four 6-Input Luts And 8 Flip-Flops ) 2. 1, 800 Kbits Of Fast Block Ram 3. Five Clock Management Tiles, Each With A Phase-Locked Loop ( Pll ) 4. 90 Dsp Slices 5. Internal Clock Speeds Exceeding 450 Mhz 6. On-Chip Analog-To-Digital Converter ( Xadc ) 7. Usb-Jtag Port For Fpga Programming And Communication 8. Serial Flash 9. Usb-Uart Bridge 10. 12-Bit Vga Output 11. Usb Hid Host For Mice, Keyboards And Memory Sticks 12. 16 User Switches 13. 16 User Leds 14. 5 User Push Buttons 15. 4-Digit 7-Segment Display, 4 Pmod Ports: 3 Standard 12-Pin Pmod Ports, 1 Dual Purpose Xadc Signal / Standard Pmod Port.
Basic Detail
Tender No 3852/A3/ECE/2019
Bidding Type Tender
Location
City GOVERNMENT COLLEGE OF ENGINEERING BODINAYAKKANUR
State Tamil Nadu
Key Dates
Publish Date 28 Nov 2019
Submission Date 13 Dec 2019
Open Date 16 Dec 2019
Finance
Tender Value Ref. Documents
Tender Fee Ref. Documents
EMD Ref. Documents
Exemption Not Available
Document List
BOQ_179855.xls
Tendernotice_1.pdf
271E67AC-54B0-41D8-80FF-24F705E749D9.html

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Tender Timeline

Nov 28, 2019
11:30 IST

Tender Published

Tender notice published.

Completed
Dec 13, 2019
17:00 IST

Bid Submission Deadline

Online submission via eProcurement portal.

Completed
Dec 16, 2019

Bid Opening Date

Technical bids will be opened and evaluated.

Completed

Tender Documents

Download All (ZIP) ↓
xls

BOQ_179855.xls

pdf

Tendernotice_1.pdf

html

271E67AC-54B0-41D8-80FF-24F705E749D9.html

TenderDetail
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