Tenders Are Invited For European Ultra-Deep Sub-Micron Beamforming Chip Ip Core For Satcom Constellations

Tenders are invited for European Ultra-Deep Sub-Micron Beamforming Chip Ip Core for Satcom Constellations (Artes at 5c.539) Objective: The objective of the activity is to develop a European beamforming chip IP core based on ultra-deep sub-micron technology for satcom constellations. Power consumption shall be minimised. Selectable waveform specific features shall be implemented to support a wide range of use cases including pre-coding and beam hopping. A test chip with compatible interfaces to high speed SerDes (Serialiser/Deserialiser) providing reliable connectivity for high throughput satellites of LEO and MEO constellations shall be designed and manufactured.Targeted Improvements: - Enabling a European or Canadian source of digital beamforming IP core for active phased array antennas.- Enabling features such as signal structure, beam hopping and precoding.- Minimised power consumption of less than 300mW per channel.Description: Due to the demand for large capacity and high spectral efficiencies, active array antennas are being increasingly employed for telecom satellites. These antennas are already playing an important role in next-generation high throughput satellite (HTS) communications together with the large low Earth orbit (LEO) and medium Earth orbit (MEO) constellations being implemented worldwide. Digital Beamforming (DBF) is considered the most flexible beamforming architecture and has advantages over analogue beamforming for receiving and transmitting wideband signals, and for multi-beam reconfigurable applications. However, it requires data converters and RF front-ends for each antenna element, increasing the complexity and power consumption.In this activity, a digital beamforming IP core will be developed, fabricated as a scaled Engineering Model test chip and tested based on ultra sub-micron technology (targeting 7nm or lower). Power consumption shall be minimised, targeting 300mW per channel. Selectable waveform specific features shall be implemented to support a wide range of use casesincluding pre-coding and beam hopping. The IP core shall enable Beamforming Networks with a total bandwidth scalable from GHz to hundreds of GHz for dynamic beam configuration, to achieve a BFIC of 32 GHz capacity with scalable frequency from L-Band to Ka-Band and frequency agnostic topology.This activity will be implemented in a phased approach where:- Phase 1 includes a comparative architectural study of at least four digital beam forming IC integration models. An evaluation of technology node implications shall be performed (e.g. leading-edge vs. trailing-edge). Phase 1 shall explore if a common architecture could support different use-cases (broadband, D2D) e.g. lowering DAC/ADC sampling rates and smart switching (bypassing digital mixing, decimation/interpolation) to maintain beam count while adjusting per-beam bandwidth. A system topology shall be evaluated and defined from the digital processor to the antenna for the placement of the beamforming network (daisy chain, star etc.). The output of Phase 1 is an evaluation of the critical IP blocks via design simulation concluding with tape-out of the design. Phase 1 budget is up to 1,200kEur.- In Phase 2 the architecture and technology for the beamforming chip IP shall be fully designed, implemented and tested to scaled engineering model level. This test chip will be representative of a scaled version of the final potential product. Scaled EM testing will include radiation exposure, thermal cycling, and performance benchmarking against existing space-grade beamforming chips.IP cores developed in this activity shall be available for further development by ESA Member State and Canadian industries at fair and reasonable market conditions. Tender Link : https://esastar-publication-ext.sso.esa.int/ESATenderActions/filter/open