Tenders are invited for Scalable Processor Array for Digital Beamforming (Artes at 5c.526) - Expro plus - Re-Issue The objective of the activity is to develop a scalable processor architecture for digital beamforming applications. An elementary processing node of a scalable telecom phased array antenna will be designed and manufactured. Beamforming algorithms will be developed and integrated into a processor array testbed comprising several nodes in order to evaluate the concept.Targeted Improvements:- 50% power and volume reduction compared state of the art digital beamforming.- 50% improvement in the thermal management system due to the distribution of the processing.Description: Digital beamforming networks offer the highest level of flexibility to telecommunication payloads but at the same time incur high costs and increased power consumption.This activity will aim at reducing the complexity of such network, with the development of a custom digital processor firmware for state-of-the-art highly integrated processing technologies. Critical functions of this development include the interconnect and networking between the processing nodes of the processor array, the selection and customisation of algorithms for digital beam weighting and aggregation, as well as the accompanying transparent and regenerative digital operations, and how they will be mapped to theprocessing nodes of the digital processor array or supported by additional hardware for direct sampling up to Ka-Band and to achieve a modular and scalable architecture that enables building of large antenna arrays. Architecture trade-offs to minimise power consumption will be carried out and the thermal and physical constraints of such a processor array will be analysed. In the initial stage of the activity, a range of technology options shall be considered to define the elementary building node of the Scalable Processor Array.As a minimum, the following technology options will be studied: (1) RF System-on-Chip (RF SoC) technology with integrated wideband, high-speed data converters. (2) FPGA technology with external data converters (3) FPGA technology with external Analog to Digital Converters (ADCs) only, while the Digital to Analog Converter (DAC) is implemented inside the digital logic. The third option will allow for the evaluation of an all-digital signal transmission chain, with the support of Multi-Gigabit Transceivers (MGTs) for the DAC.Previous work has shown that FPGA-embedded MGTs can serve as 1-bit RF DACs, acting as the interface between the digital and analogue domains.The activity places priority on overall power consumption, while ensuring no adverse effects on the RF Figures of Merit to enable the definition of an optimal architecture for both phased array payloads and phased array terminals based on the same concept. In cases where external data converters are considered, high-speed interfaces suitable for wideband Software-Defined Radio (SDR) up to Ka-band applications should be chosen. Once elementary building node are identified, the activity will design, manufacture, and test a digital processor array testbed, comprising several processing array nodes and its algorithms for digital beamforming applications to demonstrate the Scalable Processor Array. The processor array shall be scalable to several hundreds of antenna elements. A mathematical model of the processor array architecture will be developed. A testbed, comprising a representative interconnected number of processing nodes shall be developed and used to evaluate the performance.Read more Tender Link : https://esastar-publication-ext.sso.esa.int/ESATenderActions/filter/open
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